SystemVerilog Clocking Block, Event handling and Statement Waits

As I’m currently learning to do chip verification with I came across the SystemVerilog feature named Clocking blocks. It is simply put, a block that samples and pushes its inputs and outputs. A nice thing about the clocking blocks is the ability to await an input to become a given value and await the event of the next event of the clocking block, which in the following case is the posedge of the clock. This really helps me with keeping my verification code synchronously written.

interface my_interface (
    input clock
);
    logic write;
    logic read;

    clocking my_cb @(posedge clock);
        // Set `default skew`. Sample 1 step before and pushes 1 step after
        // the posedge of the clock. If no `default skew` is set the default
        // will be 1 step input and 0 step output
        default input #1 output #1;

        // Outputs can be assigned values which will be pushed to any modules
        // hooked up to the `write` logic of this interface at 1 step after the
        // posedge of the `clock`. It is WRITE-ONLY and any attempt to read the
        // current value of the output will cause an error.
        output write;

        // Inputs can NOT be assigned values but instead the value of logic `read`
        // will be sampled to the input at 1 step before the posedge of the
        // `clock`. It is READ-ONLY and any attempt to assign the input a new
        // value will cause an error.
        input read; // Input 
    endclocking

endinterface

task some_task();

    @(if_instance.my_cb); // blocks untill next posedge clock

    wait(if_instance.my_cb.read == 1); // blocks untill read has become 1

endtask